A technological reduction is a way to reduce the costs associated with a technological platform by minimizing the workload of the designers. Thus, a technological reduction of 10% allows a gain of around 20% in the total surface area of the chip on which the integrated circuits are fabricated. By way of example, the reduced version of the 120 nanometer CMOS technology is a 110 nanometer CMOS technology.
One conventional approach used for fabricating, using a reduced technology, an integrated circuit designed in a native technology, includes applying a uniform homothetic reduction to the reduced technological version over the whole of the integrated circuit. However, such a technique may lead, in the end, to transistors produced with performance characteristics that differ from the corresponding transistors designed in the native technology.